A class of memory devices called pseudo-static memory are typically memory devices that are functionally equivalent to static random access memory (SRAM) devices, but have a memory core based on conventional dynamic random access memory (DRAM) cells. In general, these memory devices can be operated in the same manner one would operate a conventional SRAM. As is well known in the art, a major distinction between the two types of memory cells is that DRAM memory cells need to be periodically refreshed to maintain the stored data, whereas SRAM memory cells do not. Consequently, pseudo-static memory devices include internal refresh circuitry to perform the necessary refresh operations of the DRAM memory core. However, refresh operations are transparent to the user, so that the devices appear as not needing refresh operations.
Although there appear to be disadvantages in employing a DRAM memory core over an SRAM memory core because of the need for periodic refresh operations to be performed, there are, however, significant advantages in other respects. For example, memory density for a DRAM memory array can be much greater than that for a SRAM memory array. In the case of a DRAM memory cell, only one transfer gate and a storage device, typically a capacitor, is necessary to store one bit of data. In contrast, conventional SRAM memory cells can have as many as six transistors per memory cell. Additionally, the simple structure and smaller size of DRAM memory cells translate into less complicated manufacturing processes, and consequently, lower fabrication costs when compared to the SRAM memory cell. In turn, memory devices employing DRAM memory cores are considerably cheaper than SRAM memory devices having equivalent memory capacities.
In an effort to integrate a DRAM memory core into a memory device that is functionally equivalent to an SRAM device, the operational differences between the two types of memory need to be addressed. For example, one difference, as previously discussed, is that DRAM memory cells need to be refreshed periodically or the data stored by the memory cells will be lost. As a result, additional circuitry must be included in the memory device to support refresh operations, but should maintain refresh transparency to the user.
Another difference between an SRAM memory core and a DRAM memory core is that once a memory access operation for a conventional DRAM memory core has begun, the entire access cycle needs to be completed or data will be lost. That is, a DRAM access cycle begins with a row of memory cells in the array being activated, and the respective charge state of the memory cells for the activated row are sensed and amplified. A particular memory cell is selected by coupling a column to an input/output line. Consequently, the memory cell at the intersection of the activated row and the selected column is accessed. At this time, data can be read from or written to the particular memory cell. Following the read or write operation, the row of memory cells is deactivated, thus, the charge states that were initially sensed and amplified are stored by the respective capacitors of the memory cells. As is generally known, the process of sensing the charge state of the memory cells is destructive. Unless the DRAM access cycle is completed by amplifying the charge state and properly deactivating the row, the data stored by the memory cells of the activated row will be lost.
In contrast, for a conventional asynchronous SRAM memory device, the SRAM sense operation is non-destructive and does not have the same type of access cycle as a conventional DRAM memory device. Consequently, random memory addresses may be asserted to the SRAM memory device without timing restriction, and data is always expected to be returned in a certain time thereafter. This time is typically referred to as the address access time tAA.
Yet another difference between memory devices having an SRAM memory core and those having a DRAM memory is that access times for DRAM memory cores are generally longer than the access times for SRAM memory cores. Asynchronous access of a DRAM memory core requires more time to provide valid data because of the time required to complete the access cycle. Although conventional DRAM devices often provide advanced access modes to decrease average access times, such as page mode access, valid memory addresses must nevertheless be provided for each data access. As a result, the minimum access time of a memory device will be limited by the setup time for providing valid and stable memory addresses, which in some cases, can take a relatively long time.
Synchronous DRAM (SDRAM) devices, which operate according to a periodic clock signal and have pipelined architectures to provide shorter average access times than asynchronous DRAM devices. Memory access times for SDRAM devices are generally lower because the pipelining of internal memory operations allow for different stages of a DRAM memory access operation to be executed in parallel, as well known in the art. This allows for new memory commands to be initiated prior to the completion of previous memory commands. As a result, conventional SDRAM devices can provide modes of operation that cannot be replicated by their asynchronous DRAM counterparts. For example, SDRAM devices have a data burst mode where new data can be output each period of a clock signal after an initial memory access without the need to provide any memory addresses other than for the first memory location. That is, data stored at the starting memory location is accessed, and data from sequential memory locations are thereafter accessed without the need to provide further memory addresses.
Despite the aforementioned disadvantages, in many instances, it is still desirable to employ memory devices having a DRAM memory core for the advantages previously discussed. Therefore, it is desirable to have circuitry that can be employed in a memory device that provides the asynchronous functionality of an SRAM device, and which accommodates the scheduled events of accessing a DRAM memory core. Moreover, in many applications, it is desirable for the circuitry to automatically detect whether an asynchronous or synchronous memory access operation is requested without the use of a flag or dedicated control signal that instructs the memory device to expect an asynchronous or synchronous memory access operation. In this manner, a memory device having such circuitry can be used as a companion device with existing types of conventional memory devices.